Hussin Abdullah · Electrical Engineer, Toronto

About

I’m a recent Electrical Engineering graduate from Carleton University. The project that really changed how I think about engineering was fabricating a CMOS chip in Carleton’s microfabrication lab and then testing it myself on an HP 4155A probe station. Seeing something go from design to physical silicon made the whole field feel a lot more real to me.

Since then, I’ve kept building projects that push my understanding further and challenge how I approach design and verification. I’ve become especially interested in catching problems early through assertions, testbenches, and verification workflows rather than finding issues after tape-out.

Some of the projects I’ve worked on include building a PCIe transaction layer model with a complete CDC sign-off flow, reducing a RISC-V SoC boot issue from a million-cycle stall down to roughly 2,500 cycles, and running a 27-point PVT sweep on a two-stage operational amplifier.

Right now, I’m looking for opportunities in design and verification where I can keep growing as an engineer, expand my knowledge, and work on problems that genuinely excite me. My goal is to keep building, keep learning, and turn that passion into a long-term career.

Skills

The toolkit I build with

Across digital design, verification, and full-custom analog layout, plus the EDA tools and languages that tie them together.

RTL & Digital Design

VerilogSystemVerilogFSM design (Moore/Mealy)Async FIFOClock gatingSync/async reset

Verification

SystemVerilog AssertionsSelf-checking testbenchesFunctional coverageLint closureCDC closureWaveform debug

Analog & IC Design

Full-custom CMOSDRC/LVSParasitic extractionCommon-centroid layoutPVT analysis45nm SOI

Protocols

PCIe TLPCredit flow controlL0/L0s/L1RISC-V (RV32I)I2CSPIUART

EDA & Lab Tools

Cadence VirtuosoSpectreQuesta/ModelSimVerilatorQuartusVivadoHP 4155A

Languages

VerilogSystemVerilogPythonMATLABC/C++TclShell

Projects

Selected work

The projects below reflect my interest in chip design and verification. Each one has been an opportunity to learn something new, apply what I know, and push my skills further. I’m always building and experimenting, so there’s more to come.

FABRICATED DIEPROBE STATION

Fabricated PRSG die under a microscope with probe needles, marked Carleton 2023

Fabricated PRSG die · probe-station bring-up at Carleton

Fabricated Silicon

Custom CMOS IC: 31-Bit Pseudo-Random Sequence Generator

Full-custom CMOS · Carleton Microfab

5-STAGE FIBONACCI LFSR100% DRC/LVS CLEANFABRICATED & TESTED

Designed and fabricated a full-custom CMOS integrated circuit, laying out the design transistor by transistor from the ground up. The chip included five flip-flops configured as a Fibonacci linear feedback shift register, an XNOR feedback path for reset functionality, an on-chip RC oscillator to generate the clock signal, and a 10-mA output driver to push the signal off-chip.

The project was taken through the complete IC design flow, from schematic capture to a 100% DRC and LVS clean layout before fabrication at the Carleton University Microfab. After fabrication, the chip was tested on a probe station, and the measured hardware results were compared directly against simulation data to validate performance.

PCIe TLPPACKET FORMAT

PCIe transaction layer packet structure

RTL & Verification

PCIe Transaction Layer Packet Generator & Checker

Verilog · SystemVerilog Assertions · CDC

5 VERILOG MODULES0 LINT WARNINGSFORMAL CDC SIGN-OFF

This project involved designing and verifying a PCIe transaction layer implemented across five Verilog modules: an encoder, decoder, six-state Moore credit-flow FSM, power management FSM with L0/L0s/L1 state gating, and a dual-clock asynchronous FIFO.

Beyond implementation, I focused heavily on verification and sign-off quality. I closed lint with zero warnings and no blanket waivers, documented every clock-domain crossing in a formal CDC report, and used SystemVerilog assertions to validate traffic and protocol behavior the same way a real verification sign-off flow would be reviewed.

View on GitHub →

RISC-V SoCPicoRV32

RISC-V SoC pre-silicon validation platform

Pre-Silicon Validation

RISC-V SoC Pre-Silicon Validation Platform

PicoRV32 · SystemVerilog · Questa

PICORV32 · 9-MODULE SOC11 SVA ASSERTIONS1M → ~2,500 CYCLES

Integrated a PicoRV32 core into a 9-module SoC featuring a power management FSM, boot ROM, RAM, and memory-mapped PMU registers.

To validate the system, I built a self-checking testbench with eleven SystemVerilog assertions covering boot sequence progression, address alignment, and PMU state reachability. A significant portion of the work involved deep waveform debugging in Questa, tracing the program counter through the boot flow to understand why the system was stalling at around one million cycles.

After isolating and fixing the issue, I reduced the boot time down to approximately 2,500 cycles and verified stable execution through simulation.

View on GitHub →

OP-AMP LAYOUT45nm SOI

Cadence Virtuoso layout of the two-stage CMOS operational amplifier

Two-stage op-amp layout · Cadence Virtuoso

Analog Layout & Sim

Two-Stage CMOS Operational Amplifier, 45nm SOI

Cadence · 45nm SOI · Spectre

45nm SOI27 PVT CORNERSPHASE MARGIN > 106°

Using Cadence, I designed and laid out a two-stage CMOS operational amplifier in a 45nm SOI process. The design is built around a differential input pair, active-load current mirrors, and an output buffer stage.

The layout was carefully sized and floorplanned using a 54-device common-centroid structure with dummy transistors to maintain symmetry and reduce mismatch effects. This was done to improve robustness across process variation and layout-dependent effects.

On the verification side, the schematic was simulated across 27 process-voltage-temperature corners (3 processes, 3 voltages, and 3 temperatures). Across all conditions, the design maintained a phase margin above 106 degrees, confirming stable operation under worst-case scenarios.

Beyond Engineering

Away from the bench

Hussin at a Manchester United match in Chicago

Soccer

I’ve been a lifelong soccer fan and have followed Manchester United for over 20 years.

Dota 2

I’ve reached Immortal rank in Dota 2, placing me in the top 1% of players in North America.

Campfire with friends by a lake at night

Outdoors

I like to step away from screens and spend time outdoors, usually unwinding in nature with friends.

Get in touch

Let’s build something.

I’m looking for design and verification opportunities where I can keep growing. If you’ve got a testbench that needs writing or a chip that needs bringing up, I’d like to hear from you.

Email me Download résumé

Emailhussin_abdullah@hotmail.com LinkedInlinkedin.com/in/hussinaltaee GitHubgithub.com/Ahsent