I designed a chip. Silicon disagreed with my simulation, so I went and asked it why.
Recent Electrical Engineering grad from Carleton University, headed toward mixed-signal and AMS verification roles — RTL, SystemVerilog Assertions, and a fabricated CMOS chip to show I've done this past a testbench.
From schematic to silicon, then back to the testbench
Most of my degree was simulations that behaved. The interesting part started the day I built something physical and it didn't.
I'm an electrical engineer out of Carleton University, and the project that actually changed how I think about this field wasn't a course — it was fabricating a CMOS chip in Carleton's microfab, then sitting at a probe station with an HP 4155A trying to explain why the silicon clock didn't match my simulation. Power delivery, component tolerance, signal integrity — the answer is usually "a little bit of everything," and figuring out which bit is most of the job.
Since then I've drifted toward verification — writing the assertions and testbenches that catch that gap before it reaches silicon instead of after. I've built a PCIe transaction-layer model with a full CDC sign-off package, brought a RISC-V SoC's boot sequence down from a million-cycle hang to 2,500 cycles, and run a 27-point PVT sweep on an op-amp until I trusted every corner of it.
Right now I'm applying to mixed-signal and AMS verification roles, and paying the bills with a data-entry job where I somehow ended up writing a 32-issue defect report on a government appointment system. Old habits.
Work Experience
- Audited a new in-house appointment-management system end to end and wrote a structured 32-issue defect and improvement report, then presented findings to drive the remediation backlog.
- Built and maintained Excel tracking databases for client follow-ups and training-funding sources, logging multi-attempt outreach with dated outcomes across all assigned accounts.
Four projects, one obsession: catching the gap between what you simulated and what you built.
Everything below is real — fabricated silicon, lint-clean RTL, and a CDC report I'd defend in an interview.
Custom CMOS IC — 31-Bit Pseudo-Random Sequence Generator
A full-custom CMOS chip, laid out transistor by transistor: five flip-flops in a Fibonacci LFSR, XNOR feedback, an on-chip RC oscillator, and a 10 mA driver to get the signal off the die. I took it from schematic to 100% DRC/LVS-clean layout, fabricated it at Carleton's microfab, then sat at a probe station and watched the real clock disagree with my simulation — the most useful debugging lesson of my degree.
PCIe Transaction Layer Packet Generator & Checker
Five synthesizable Verilog modules implementing the PCIe transaction layer — encoder, decoder, a 6-state Moore credit-flow FSM, a power FSM with L0/L0s/L1 gating, and a dual-clock async FIFO sized off a worst-case burst analysis. Lint closed to zero warnings with no blanket waivers, every clock-domain crossing got a formal CDC writeup, and SVA in Questa verified the traffic the way an actual sign-off package gets reviewed.
RISC-V SoC Pre-Silicon Validation Platform
A PicoRV32 core wired into a 9-module SoC — power-management FSM, boot ROM, RAM, memory-mapped PMU registers — behind a self-checking testbench with 11 SVA assertions watching boot progression, address alignment, and PMU-state reachability. The best two hours of this project were tracing a program counter through Questa waveforms to find why boot was hanging at a million cycles, then watching it finish in 2,500.
Two-Stage CMOS Operational Amplifier, 45nm SOI
A two-stage CMOS op-amp — differential pair, active-load mirrors, output buffer — sized and floor-planned as a 54-device common-centroid array to stay symmetric under mismatch. I ran it through all 27 PVT corners, three process splits by three voltages by three temperatures, and it held phase margin above 106° and gain variation under 11% everywhere I looked.
The rest of the spec sheet
Flew to Chicago for the Summer Series because some signals are worth chasing in person, not just on a waveform.
Top ~0.1% bracket. Reading the state of a chaotic system and predicting what breaks next transfers surprisingly well to RTL.
Most weekends end with a fire pit, a lake, and zero spreadsheets — the best place I know to stop debugging and let an idea land.
Let's talk.
I'm looking for full-time mixed-signal and AMS verification roles — Toronto-based, open to relocating. If you've got a testbench that needs writing or a chip that needs bringing up, I'd like to hear about it.